Isolation region forming methods

ABSTRACT

In one aspect, the invention includes an isolation region forming method comprising: a) forming an oxide layer over a substrate; b) forming a nitride layer over the oxide layer, the nitride layer and oxide layer having a pattern of openings extending therethrough to expose portions of the underlying substrate; c) etching the exposed portions of the underlying substrate to form openings extending into the substrate; d) after etching the exposed portions of the underlying substrate, removing portions of the nitride layer while leaving some of the nitride layer remaining over the substrate; and e) after removing portions of the nitride layer, forming oxide within the openings in the substrate, the oxide within the openings forming at least portions of isolation regions.  
     In another aspect, the invention includes an isolation region forming method comprising: a) forming a silicon nitride layer over a substrate; b) forming a masking layer over the silicon nitride layer; c) forming a pattern of openings extending through the masking layer to the silicon nitride layer; d) extending the openings through the silicon nitride layer to the underlying substrate, the silicon nitride layer having edge regions proximate the openings and having a central region between the edge regions; e) extending the openings into the underlying substrate; f) after extending the openings into the underlying substrate, reducing a thickness of the silicon nitride layer at the edge regions to thin the edge regions relative to the central region; and g) forming oxide within the openings.

TECHNICAL FIELD

[0001] The invention pertains to methods of forming isolation regionsand can have particular application to methods of forming shallow trenchisolation regions.

BACKGROUND OF THE INVENTION

[0002] In modern semiconductor device applications, numerous individualdevices are packed onto a single small area of a semiconductorsubstrate. Many of these individuals devices need to be electricallyisolated from one another. One method of accomplishing such isolation isto form a trenched isolation region between adjacent devices. Suchtrenched isolation region will generally comprise a trench or cavityformed within the substrate and filled with an insulative material, suchas, for example, silicon dioxide. Trench isolation regions are commonlydivided into three categories: shallow trenches (trenches less thanabout one micron deep); moderate depth trenches (trenches of about oneto about three microns deep); and deep trenches (trenches greater thanabout three microns deep).

[0003] Prior art methods for forming trench structures are describedwith reference to FIGS. 1-12. Referring to FIG. 1, a semiconductor waferfragment 10 is shown at a preliminary stage of a prior art processingsequence. Wafer fragment 10 comprises a semiconductive material 12 uponwhich is formed a layer of oxide 14, a layer of nitride 16, and apatterned layer of photoresist 18. Semiconductive material 12 commonlycomprises monocrystalline silicon which is lightly doped with aconductivity-enhancing dopant. To aid in interpretation of the claimsthat follow, the term “semiconductive substrate” is defined to mean anyconstruction comprising semiconductive material, including, but notlimited to, bulk semiconductive materials such as a semiconductive wafer(either alone or in assemblies comprising other materials thereon), andsemiconductive material layers (either alone or in assemblies comprisingother materials). The term “substrate” refers to any supportingstructure, including, but not limited to, the semiconductive substratesdescribed above.

[0004] Oxide layer 14 typically comprises silicon dioxide, and nitridelayer 16 typically comprises silicon nitride. Nitride layer 16 isgenerally from about 400 Angstroms thick to about 920 Angstroms thick.

[0005] Referring to FIG. 2, patterned photoresist layer 18 is used as amask for an etching process. The etch is typically conducted utilizingdry plasma conditions and CH₂F₂/CF₄ chemistry. Such etching effectivelyetches both silicon nitride layer 16 and pad oxide layer 14 to formopenings 20 extending therethrough. Openings 20 comprise peripheriesdefined by nitride sidewalls 17 and oxide sidewalls 15. The etchingstops upon reaching silicon substrate 12.

[0006] Referring to FIG. 3, a second etch is conducted to extendopenings 20 into silicon substrate 12. The second etch is commonlyreferred to as a “trench initiation etch.” The trench initiation etch istypically a timed dry plasma etch utilizing CF₄/HBr, and typicallyextends openings 20 to less than or equal to about 500 Angstroms intosubstrate 12. A purpose of the trench initiation etch can be to clean anexposed surface of silicon substrate 12 within openings 20 (i.e., toremove defects and polymer material) prior to final trenching intosubstrate 12. Another purpose of the trench initiation etch can be toform polymer over exposed sidewall edges 15 and 17 of oxide layer 14 andnitride layer 16, respectively. Such polymer can alleviate erosion ofsidewall edges 15 and 17 during subsequent etching of substrate 12.

[0007] Referring to FIG. 4, a third etch is conducted to extend openings20 further into substrate 12 and thereby form trenches within substrate12. Extended openings 20 comprise a periphery 22 defined by substrate12. The third etch typically utilizes an etchant consisting entirely ofHBr, and is typically a timed etch. The timing of the etch is adjustedto form trenches within substrate 12 to a desired depth. For instance,if openings 20 are to be shallow trenches, the third etch will be timedto extend openings 20 to a depth of less than or equal to about onemicron.

[0008] Referring to FIG. 5, photoresist layer 18 (FIG. 4) is removed anda first oxide layer 24 is thermally grown within openings 20 and alongthe periphery 22 (FIG. 4) defined by silicon substrate 12. The growth ofoxide layer 24 can form small bird's beak regions 26 underlying sidewalledges 17 of nitride layer 16.

[0009] Referring to FIG. 6, a high density plasma oxide 28 is formed tofill openings 20 (FIG. 5) and overlie nitride layer 16. High densityplasma oxide 28 merges with oxide layer 24 (FIG. 5) to form oxide plugs30 within openings 20 (FIG. 5). Oxide plugs 30 have laterally outermostperipheries 33 within openings 20.

[0010] Referring to FIG. 7, wafer fragment 10 is subjected toplanarization (such as, for example, chemical-mechanical polishing) toplanarize an upper surface of oxide plugs 30. The planarization stops atan upper surface of nitride layer 16.

[0011] Referring to FIG. 8, nitride layer 16 is removed to expose padoxide layer 14 between oxide plugs 30.

[0012] Referring to FIG. 9, pad oxide layer (FIG. 8) is removed. Theremoval of the pad oxide layer leaves dips 32 at edges of oxide plugs30.

[0013] Referring to FIG. 10, a sacrificial oxide layer 34 is grown oversubstrate 12 and between oxide plugs 30.

[0014] Referring to FIG. 11, sacrificial oxide layer 34 (FIG. 10) isremoved. Formation and removal of sacrificial oxide layer 34 can beutilized to clean a surface of substrate 12 between oxide plugs 30. Assuch surface of substrate 12 can be ultimately utilized to form anactive area of a transistor device, it is desired that the surface besubstantially free of defects. The removal of sacrificial oxide layer 34can also undesirably exacerbate dips 32.

[0015] Referring to FIG. 12, a silicon dioxide layer 36 is regrownbetween oxide plugs 30, and a polysilicon layer 38 is formed over oxideplugs 30 and oxide layer 36. Polysilicon layer 38 can ultimately beformed into a word line comprising transistor gate regions. Suchtransistor gate regions can lie between oxide plugs 30. Plugs 30 canthen function as trenched isolation regions between transistor devices.Dips 32 can undesirably result in formation of parasitic devicesadjacent the transistor devices and ultimately have an effect oflowering a threshold voltage for the transistor devices. Accordingly, itwould be desirable to alleviate dips 32. Dips 32 can also interfere withsubsequent fabrication processes and, for this reason as well, it wouldbe desirable to alleviate dips 32.

SUMMARY OF THE INVENTION

[0016] In one aspect, the invention encompasses an isolation regionforming method. An oxide layer is formed over a substrate. A nitridelayer is formed over the oxide layer. The nitride layer and oxide layerhave a pattern of openings extending therethrough to expose portions ofthe underlying substrate. The exposed portions of the underlyingsubstrate are etched to form openings extending into the substrate.After etching the exposed portions of the substrate, portions of thenitride layer are removed while leaving some of the nitride layerremaining over the substrate. After removing portions of the nitridelayer, oxide is formed within the openings in the substrate. The oxidewithin the openings forms at least portions of isolation regions.

[0017] In another aspect, the invention encompasses another embodimentisolation region forming method. A silicon nitride layer is formed overa substrate. A masking layer is formed over the silicon nitride layer. Apattern of openings is formed to extend through the masking layer and tothe silicon nitride layer. The openings are extended through the siliconnitride layer to the underlying substrate. The silicon nitride layer hasedge regions proximate the openings and has a central region between theedge regions. The openings are extended into the underlying substrate.After extending the openings into the underlying substrate, a thicknessof the silicon nitride layer is reduced at the edge regions to thin theedge regions relative to the central region. Oxide is formed within theopenings that are extended into the substrate. The oxide within theopenings forms at least portions of isolation regions.

BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Preferred embodiments of the invention are described below withreference to the following accompanying drawings.

[0019]FIG. 1 is a diagrammatic, fragmentary, cross-sectional view of asemiconductor wafer fragment at a preliminary step of a prior artprocessing sequence.

[0020]FIG. 2 shows the FIG. 1 wafer fragment at a prior art processingstep subsequent to that of FIG. 1.

[0021]FIG. 3 shows the FIG. 1 wafer fragment at a prior art processingstep subsequent to that of FIG. 2.

[0022]FIG. 4 shows the FIG. 1 wafer fragment at a prior art processingstep subsequent to that of FIG. 3.

[0023]FIG. 5 shows the FIG. 1 wafer fragment at a prior art processingstep subsequent to that of FIG. 4.

[0024]FIG. 6 shows the FIG. 1 wafer fragment at a prior art processingstep subsequent to that of FIG. 5.

[0025]FIG. 7 shows the FIG. 1 wafer fragment at a prior art processingstep subsequent to that of FIG. 6.

[0026]FIG. 8 shows the FIG. 1 wafer fragment at a prior art processingstep subsequent to that of FIG. 7.

[0027]FIG. 9 shows the FIG. 1 wafer fragment at a prior art processingstep subsequent to that of FIG. 8.

[0028]FIG. 10 shows the FIG. 1 wafer fragment at a prior art processingstep subsequent to that of FIG. 9.

[0029]FIG. 11 shows the FIG. 1 wafer fragment at a prior art processingstep subsequent to that of FIG. 10.

[0030]FIG. 12 shows the FIG. 1 wafer fragment at a prior art processingstep subsequent to that of FIG. 11.

[0031]FIG. 13 is a schematic, fragmentary, cross-sectional view of asemiconductor wafer fragment in process according to a first embodimentmethod of the present invention. The processing step illustrated in FIG.13 is subsequent to the prior art processing step shown in FIG. 3.

[0032]FIG. 14 shows the FIG. 13 wafer fragment at a processing stepsubsequent to that of FIG. 13.

[0033]FIG. 15 shows the FIG. 13 wafer fragment at a processing stepsubsequent to that of FIG. 14.

[0034]FIG. 16 shows the FIG. 13 wafer fragment at a processing stepsubsequent to that of FIG. 15.

[0035]FIG. 17 is a schematic, fragmentary, cross-sectional view of asemiconductor wafer fragment in process according to a second embodimentmethod of the present invention. The wafer fragment of FIG. 16 is shownat a processing step subsequent to the prior art processing step of FIG.4.

[0036]FIG. 18 shows the FIG. 17 wafer fragment at a processing stepsubsequent to that of FIG. 17.

[0037]FIG. 19 shows the FIG. 17 wafer fragment at a processing stepsubsequent to that of FIG. 18.

[0038]FIG. 20 shows the FIG. 17 wafer fragment at a processing stepsubsequent to that of FIG. 19.

[0039]FIG. 21 shows the FIG. 17 wafer fragment at a processing stepsubsequent to that of FIG. 20.

[0040]FIG. 22 is a schematic, fragmentary, cross-sectional view of asemiconductor wafer fragment in process according to a third embodimentmethod of the present invention. The wafer fragment of FIG. 20 is shownat a processing step subsequent to the prior art processing step of FIG.4.

[0041]FIG. 23 shows the FIG. 22 wafer fragment at a processing stepsubsequent to that of FIG. 22.

[0042]FIG. 24 shows the FIG. 22 wafer fragment at a processing stepsubsequent to that of FIG. 23.

[0043]FIG. 25 shows the FIG. 22 wafer fragment at a processing stepsubsequent to that of FIG. 24.

[0044]FIG. 26 is a schematic, fragmentary, cross-sectional view of asemiconductor wafer fragment in process according to a fourth embodimentmethod of the present invention. The wafer fragment of FIG. 26 is shownat a processing step subsequent to the prior art processing step of FIG.3.

[0045]FIG. 27 shows the FIG. 26 wafer fragment at a processing stepsubsequent to that of FIG. 26.

[0046]FIG. 28 shows the FIG. 26 wafer fragment at a processing stepsubsequent to that of FIG. 27.

[0047]FIG. 29 shows the FIG. 26 wafer fragment at a processing stepsubsequent to that of FIG. 28.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0048] This disclosure of the invention is submitted in furtherance ofthe constitutional purposes of the U.S. Patent Laws “to promote theprogress of science and useful arts” (Article 1, Section 8).

[0049] The present invention encompasses methods which can alleviate thedips 32 described above with reference to the prior art processing shownin FIGS. 1-12. A first embodiment of the present invention is describedwith reference to FIGS. 13-16. In describing the first embodiment,similar numbering to that utilized above in describing the prior artprocessing of FIGS. 1-12 will be used, with differences indicated bysuffix “a” or by different numerals.

[0050]FIG. 13 illustrates a semiconductor wafer fragment 10 a at apreliminary stage of the first embodiment method. Specifically, waferfragment 10 a is illustrated at a processing step subsequent to theprior art step of FIG. 3. Wafer fragment 10 a comprises a semiconductivesubstrate 12, an oxide layer 14, a nitride layer 16, and a photoresistlayer 18. Openings 40 extend through oxide layer 14 and nitride layer 16and into substrate 12. Oxide layer 14 and nitride layer 16 ultimatelyfunction as masking layers during formation of an isolation region, andso can be referred to as a first masking layer 14 and a second maskinglayer 16.

[0051] The formation of openings 40 can be initiated by processingidentical to that described above with reference to prior art FIG. 3.Specifically, openings 20 (FIG. 3) are formed by transferring a patternfrom photoresist layer 18 through first and second masking layers 14 and16. Openings 20 (FIG. 3) are then extended into openings 40 by etchingphotoresist layer 18. Such etching reduces a horizontal width ofphotoresist layer 18 and thereby exposes portions of underlying secondmasking layer 16. The etch of photoresist layer 18 can comprise, forexample, a dry etch utilizing a mixture of an oxygen-containing materialand He. The oxygen-containing material can comprise, for example, O₂present in a concentration greater than or equal to about 10%.Alternatively, the etch can be a dry etch utilizing 100% O₂. The etchwill generally remove photoresist faster with higher concentrations ofO₂ utilized in the etch than with lower concentrations of O₂. Inembodiments in which masking layers 14 and 16 comprise oxide andnitride, respectively, the above-described etch conditions can alsoremove polymer from exposed portions of nitride layer 16 and oxide layer14. Such polymer is described in the “Background” section of thisdisclosure with reference to FIG. 3, and is described as protectingnitride sidewalls 17 and oxide sidewalls 15 during a silicon etchdescribed with reference to FIG. 4. Accordingly, removal of such polymerlayer can increase susceptibility of layers 14 and 16 to a subsequentsilicon etch.

[0052] Referring to FIG. 14, wafer fragment 10 a is subjected to asilicon etch, such as, for example, the HBr etch described above withreference to FIG. 4. Such etch extends openings 40 into substrate 12 andalso removes exposed portions of nitride layer 16 and oxide layer 14.Accordingly, the etch moves a furthest lateral periphery of the secondmasking layer (defined by sidewalls 17) outward from the opening withoutreducing a thickness of the second masking layer. After the etching,openings 40 comprise a step 42 (corresponding to rounded corners) belowoxide layer 14. Step 42 defines a region where a wider upper portion ofan opening 40 joins to a narrower lower portion of the opening 40.

[0053] Referring to FIG. 15, photoresist layer 18 (FIG. 14) is removedand an oxide layer 44 is thermally formed within openings 40 by, forexample, a process analogous to that discussed above with reference tothe prior art wafer fragment of FIG. 5. An exemplary process forthermally growing oxide is to expose wafer fragment 10 a to a mixture ofAr and O₂, at a temperature of about 1050° C. and a pressure of about 1atmosphere, for a time of from about 10 to about 15 minutes. After theformation of oxide layer 44, subsequent processing analogous to thatdiscussed above with reference to FIG. 6-12 can then be conducted toform isolation regions within openings 40.

[0054]FIG. 16 illustrates wafer fragment 10 a after such subsequentprocessing. Specifically, FIG. 16 shows wafer fragment 10 a afterisolation regions 46 have been formed within openings 40 (FIG. 15), andafter a polysilicon layer 38 is provided over the isolation regions. Asshown, steps 42 define an outer lateral periphery of isolation regions46. Such outer periphery is further outward than an outward periphery 33of isolation regions 30 of FIG. 12. Such has resulted in the alleviation(shown as elimination) of dips 32 (FIG. 12) of the prior art isolationregions.

[0055] A second embodiment method of the present invention is describedwith reference to FIGS. 17-21. In describing the second embodiment,similar numbering to that utilized in describing the prior art of FIGS.1-12 will be used, with differences indicated by the suffix “b” or bydifferent numerals.

[0056] Referring to FIG. 17, a wafer fragment 10 b is illustrated at apreliminary processing step of the second embodiment method.Specifically, wafer fragment 10 b is illustrated at a processing stepsubsequent to the prior art step illustrated in FIG. 4, with photoresistlayer 18 (FIG. 4) having been removed. Wafer fragment 10 b comprisessilicon substrate 12, oxide layer 14, and nitride layer 16, with layers14 and 16 alternatively being referred to as first and second maskinglayers, respectively. Openings 50 extend through nitride layer 16 andoxide layer 14, and into substrate 12. Openings 50 can be formed inaccordance with the methods described above with reference to FIG. 4 forforming openings 20.

[0057] Referring to FIG. 18, wafer fragment 10 b is exposed to a wetetch which isotropically etches nitride layer 16 relative to oxide layer14 and silicon substrate 12. Such etch can comprise, for example, a dipof wafer fragment 10 b into phosphoric acid (H₃PO₄) at a temperature of150° C. and ambient pressure. Such dip has been found to consistentlyetch silicon nitride at a rate of about 55 Angstroms per minute. Theetch reduces a thickness of nitride layer 16 and at the same time movessidewalls 17 of nitride layer 16 outwardly from openings 50 to widen atop portion of openings 50. The nitride etch thus results in theformation of steps 52 within openings 50. Steps 52 define a locationwhere a wider upper portion of openings 50 joins a narrower lowerportion of openings 50. Steps 52 have an upper surface comprisingsilicon oxide of oxide layer 14.

[0058] Preferably, nitride layer 16 has a thickness of at least about600 Angstroms over substrate 12 after the above-discussed phosphoricacid etch. If remaining nitride layer 16 is less than 600 Angstromsthick, it is found to be less capable of functioning as an etch stop forsubsequent etching (such as the etching described with reference toprior art FIG. 7). Typically, from about 50 Angstroms to about 250Angstroms of nitride is removed from nitride layer 16 during thephosphoric acid etch.

[0059] Referring to FIG. 19, substrate 10 b is exposed to a hydrofluoricacid etchant to selectively remove portions of pad oxide layer 14. Theremoval of portions of pad oxide 14 drops steps 52 to an upper surfaceof substrate 12. In some applications, it can be equally preferable toforego such pad oxide etch and proceed directly to the oxidationdescribed with reference to FIG. 20.

[0060] Referring to FIG. 20, wafer fragment 10 b is exposed to oxidizingconditions which form an oxide layer 56 within openings 50. Oxide layer56 overlies steps 52.

[0061] Referring to FIG. 21, wafer fragment 10 b is exposed tosubsequent processing analogous to the prior art processing describedabove with reference to FIGS. 6-12 to form isolation regions 58 and apolysilicon layer 38 overlying isolation regions 58. As shown, steps 52define an outer lateral periphery of isolation regions 58. Such outerperiphery is further outward than an outer periphery 33 of isolationregions 30 of FIG. 12. Such has resulted in the alleviation (shown aselimination) of dips 32 (FIG. 12) of the prior art isolation regions.

[0062] A third embodiment of the invention is described with referenceto FIGS. 22-25. In describing the third embodiment, similar numbering tothat utilized above in describing the first two embodiments will beused, with differences indicated by the suffix “c” or by differentnumerals.

[0063] Referring to FIG. 22, a wafer fragment 10 c is shown at apreliminary stage of the third embodiment processing. Wafer fragment 10c is shown at a processing step subsequent to that of FIG. 4, with aphotoresist layer 18 (FIG. 4) having been removed. Wafer fragment 10 ccomprises a semiconductor substrate 12, a pad oxide layer 14, and asilicon nitride layer 16, with layers 14 and 16 alternatively beingreferred to as first and second masking layers, respectively. Openings60 extend through layers 16 and 14, and into substrate 12.

[0064] Referring to FIG. 23, nitride layer 16 is subjected to a facetetch to reduce a thickness of portions of nitride layer 16 proximateedges 17. The facet etching can comprise, for example, a plasma etchutilizing argon in combination with a fluorine-containing compound(e.g., CH₂F₂). Preferably, the mixture of argon and fluorine-containinggas comprises less than or equal to about 5% fluorine-containing gas (byvolume). An exemplary pressure condition of the facet-etching is fromabout 2 mTorr to about 20 mTorr.

[0065] Either before or after the facet etching, wafer fragment 10 c issubjected to HF etching to remove portions of oxide layer 14 from underedges 17 of nitride layer 16. The removal of the portions of oxide layer14 leaves exposed corners 61 of an upper surface of silicon substrate12.

[0066] Referring to FIG. 24, wafer fragment 10 c is subjected tooxidation which forms an oxide layer 62 within openings 60. The facetetching of nitride layer 16 prior to thermal oxidation results inrounding of corners 61 due to lifting of the edges of faceted nitridelayer 16. The rounding of corners 61 is more pronounced than rounding ofany analogous corners in the prior art processing described above withreference to FIG. 5.

[0067] Subsequent processing analogous to the prior art processing ofFIGS. 6-12 results in a structure shown in FIG. 25 comprising isolationregions 64 and a polysilicon layer 66 overlying isolation region 64. Itis noted that the faceted edges of nitride layer 16 can lead tooverhanging oxide ledges (not shown) of the isolation oxide formedduring application of the subsequent processing of FIGS. 6-12 to thestructure of FIG. 24. If such overhanging oxide ledges are formed, theyare preferably removed prior to formation polysilicon layer 66. Suchoverhanging oxide ledges can be removed by, for example,chemical-mechanical polishing of the isolation oxide.

[0068]FIG. 25 illustrates that rounded corners 61 have alleviatedformation of dips 32 (FIG. 12) of the prior art.

[0069] A fourth embodiment of the present invention is described withreference to FIGS. 26-29. In describing the fourth embodiment, similarnumbering to that utilized above in describing the first threeembodiments will be used, with differences indicated by the suffix “d”or by different numerals.

[0070] Referring to FIG. 26, a wafer fragment 10 d is shown at apreliminary stage of the fourth embodiment method. Specifically, waferfragment 10 d is shown at a processing step subsequent to the prior artprocessing step of FIG. 3. Wafer fragment 10 d comprises a substrate 12,a pad oxide layer 14 and a nitride layer 16, with layers 14 and 16alternatively being referred to as first and second masking layers,respectively. Additionally, substrate 12 comprises a photoresist layer18 and openings 70 extending through layers 18, 16 and 14, and intosubstrate 12. Openings 70 can be formed by, for example, prior artmethods described above for forming openings 20 of FIG. 3. Afterformation of openings 70, photoresist layer 18 is etched back by, forexample, a dry etch utilizing an oxygen-containing material, such as theetch described above with reference to FIG. 13. Such etch exposesportions of nitride layer 16, while leaving other portions covered byphotoresist 18.

[0071] Referring to FIG. 27, the exposed portions of nitride layer 16are exposed to addition etching conditions, such as, for example, aphosphoric acid etch as described above with reference to FIG. 18, toreduce a thickness of the exposed portions of the nitride layer.Specifically, the original nitride layer had a thickness of “A” (whichremains the thickness of an unetched central region of the nitridelayer), and the etched portion of the nitride layer (the edge regions)has a thickness of “B”. Preferably, “B” is about one-half “A”. Theetching does not move the furthest lateral periphery of nitride layer 16(defined by sidewall 17) outward from openings 70.

[0072] Referring to FIG. 28, wafer fragment 10 d is exposed to oxidizingconditions which grow an oxide layer 72 within openings 70. The thinnedregions of nitride layer 16 are relatively easily lifted by the growingoxide such that “birds beaks” are formed under the thinned regions ofnitride layer 16. The birds beaks are extended relative to any birdsbeaks formed during the prior art processing described above withreference to FIG. 5. Photoresist layer 18 is removed prior to theexposure of wafer fragment 10 d to oxidizing conditions.

[0073] Referring to FIG. 29, wafer fragment 10 d is exposed tosubsequent processing conditions analogous to the prior art processingdescribed above with reference to FIGS. 6-12 to form isolation regions74 and polysilicon layer 38 overlying isolation regions 34. It is notedthat the reduced-thickness edges of nitride layer 16 can lead tooverhanging oxide ledges (not shown) of the isolation oxide formedduring application of the subsequent processing of FIGS. 6-12 to thestructure of FIG. 27. If such overhanging oxide ledges are formed, theyare preferably removed prior to formation polysilicon layer 38. Suchoverhanging oxide ledges can be removed by, for example,chemical-mechanical polishing of the isolation oxide.

[0074] The processing of FIGS. 26-29 alleviates the prior art dips 32described above in the “Background” section (shown as elimination ofdips 32).

[0075] In compliance with the statute, the invention has been describedin language more or less specific as to structural and methodicalfeatures. It is to be understood, however, that the invention is notlimited to the specific features shown and described, since the meansherein disclosed comprise preferred forms of putting the invention intoeffect. The invention is, therefore, claimed in any of its forms ormodifications within the proper scope of the appended claimsappropriately interpreted in accordance with the doctrine ofequivalents.

1. An isolation region forming method comprising: forming openingsthrough first and second masking layers over a substrate, the secondmasking layer being over the first masking layer; after forming theopenings, removing portions of the second masking layer while leavingsome of the second masking layer remaining over the substrate; and afterremoving portions of the second masking layer, forming an insulativematerial within the etch openings, the insulative material within theetch openings forming at least portions of isolation regions.
 2. Themethod of claim 1 wherein the first masking layer comprises silicondioxide and the second masking layer comprises silicon nitride.
 3. Themethod of claim 1 wherein the substrate comprises silicon and theforming insulative material comprises: thermally growing a first silicondioxide layer from the substrate within the openings; and depositing asecond silicon dioxide layer within the openings and over the firstsilicon dioxide layer.
 4. The method of claim 1 wherein the removingportions of the second masking layer reduces a thickness of the secondmasking layer without moving a lateral periphery of the second maskinglayer outward from the opening.
 5. The method of claim 1 wherein theremoving portions of the second masking layer moves a lateral peripheryof the second masking layer outward from the opening without reducing athickness of the second masking layer.
 6. The method of claim 1 whereinthe removing portions of the second masking layer moves a lateralperiphery of the second masking layer outward from the opening andreduces a thickness of the second masking layer.
 7. The method of claim1 further comprising forming a patterned layer of photoresist over thesecond masking layer before forming the openings through the first andsecond masking layers, the forming the openings through the first andsecond masking layers comprising transferring a pattern from thepatterned photoresist to the first and second masking layers, at leastsome of the photoresist remaining over the second masking layer duringthe removing portions of the second masking layer.
 8. The method ofclaim 1 further comprising: forming a patterned layer of photoresistover the second masking layer before forming the openings through thefirst and second masking layers, the forming the openings through thefirst and second masking layers comprising transferring a pattern fromthe patterned photoresist to the first and second masking layers; andremoving the photoresist from over the second masking layer prior to theremoving portions of the second masking layer.
 9. An isolation regionforming method comprising: forming openings through first masking andsecond masking layers and into a substrate underlying the first andsecond masking layers, the second masking layer being over the firstmasking layer; removing portions of the second masking layer whileleaving some of the second masking layer remaining over the substrate;and after removing portions of the second masking layer, thermallyoxidizing the substrate within the openings to form an oxide layerwithin the openings, the oxide layer within the openings forming atleast portions of isolation regions.
 10. The method of claim 9 whereinthe first masking layer comprises silicon dioxide and the second maskinglayer comprises silicon nitride.
 11. The method of claim 9 wherein thesubstrate comprises silicon and further comprising depositing a secondsilicon dioxide layer within the openings and over the thermally grownoxide layer.
 12. The method of claim 9 wherein the removing portions ofthe second masking layer reduces a thickness of the second masking layerwithout moving a lateral periphery of the second masking layer outwardfrom the opening.
 13. The method of claim 9 wherein the removingportions of the second masking layer moves a lateral periphery of thesecond masking layer outward from the opening without reducing athickness of the second masking layer.
 14. The method of claim 9 whereinthe removing portions of the second masking layer moves a lateralperiphery of the second masking layer outward from the opening andreduces a thickness of the second masking layer.
 15. The method of claim9 further comprising forming a patterned layer of photoresist over thesecond masking layer before forming the openings through the first andsecond masking layers, the forming the openings through the first andsecond masking layers comprising transferring a pattern from thepatterned photoresist to the first and second masking layers, at leastsome of the photoresist remaining over the second masking layer duringthe removing portions of the second masking layer.
 16. The method ofclaim 9 further comprising: forming a patterned layer of photoresistover the second masking layer before forming the openings through thefirst and second masking layers, the forming the openings through thefirst and second masking layers comprising transferring a pattern fromthe patterned photoresist to the first and second masking layers; andremoving the photoresist from over the second masking layer prior to theremoving portions of the second masking layer.
 17. An isolation regionforming method comprising: forming a first masking layer over asubstrate; forming a second masking layer over the first masking layer,the first and second masking layers having a pattern of openingsextending therethrough to expose portions of the underlying substrate;etching the exposed portions of the underlying substrate to formopenings extending into the substrate; after etching the exposedportions of the underlying substrate, removing portions of the secondmasking layer while leaving some of the second masking layer remainingover the substrate; and after removing portions of the second maskinglayer, forming an insulative material within the openings in thesubstrate, the insulative material within the openings forming at leastportions of isolation regions.
 18. The method of claim 17 wherein thefirst masking layer comprises silicon dioxide and the second maskinglayer comprises silicon nitride.
 19. The method of claim 17 wherein thesecond masking layer comprises lateral sidewalls along the openingsextending through the second masking layer, and wherein the removingportions of the second masking layer displaces the lateral sidewallsaway from the openings.
 20. The method of claim 17 wherein the secondmasking layer comprises a thickness over the first masking layer, andwherein the removing portions of the second masking layer reduces thethickness of at least some of the remaining second masking layer. 21.The method of claim 17 wherein the second masking layer comprises athickness over the first masking layer, and wherein the removingportions of the second masking layer reduces the thickness of anentirety of the remaining second masking layer.
 22. The method of claim17 wherein the removing portions of the second masking layer comprisesfacet etching the second masking layer.
 23. The method of claim 17further comprising: after removing portions of the second masking layer,etching the substrate to extend the openings formed in the substratefurther into the substrate.
 24. An isolation region forming methodcomprising: forming a masking layer over a substrate; forming a patternof openings extending through the masking layer and into the underlyingsubstrate; after forming the openings, facet etching the first maskinglayer; and after the facet etching, forming insulative material withinthe openings extended into the substrate, the insulative material withinthe openings forming at least portions of isolation regions.
 25. Themethod of claim 24 wherein the masking layer comprises silicon nitride.26. The method of claim 24 wherein the substrate comprises silicon andthe forming insulative material comprises: thermally growing a firstsilicon dioxide layer from the substrate within the openings; anddepositing a second silicon dioxide layer within the openings and overthe first silicon dioxide layer.
 27. An isolation region forming methodcomprising: forming a masking layer over a substrate; forming a patternof openings extending through the masking layer and into the underlyingsubstrate, the first masking layer having edge regions proximate theopenings and having a central region between the edge regions; afterextending the openings into the underlying substrate, reducing athickness of the first layer at the edge regions to thin the edgeregions relative to the central region; and forming insulative materialwithin the openings extended into the substrate, the insulative materialwithin the openings forming at least portions of isolation regions. 28.The method of claim 27 wherein the masking layer comprises siliconnitride.
 29. The method of claim 27 wherein the substrate comprisessilicon and the forming insulative material comprises: thermally growinga first silicon dioxide layer from the substrate within the openings;and depositing a second silicon dioxide layer within the openings andover the first silicon dioxide layer.
 30. The method of claim 27 furthercomprising forming a patterned photoresist layer over the masking layer,and wherein the forming openings comprises transferring a pattern fromthe patterned photoresist layer to the masking layer, the reducing thethickness of the silicon nitride layer at the edge regions comprising:removing a portion of the photoresist overlying the masking layer edgeregions while leaving another portion of the photoresist overlying themasking layer central region; and after removing the portion of thephotoresist, and while said other portion of the photoresist is over themasking layer central region, exposing the masking layer to etchingconditions which reduce the thickness of the masking layer at the edgeregions.
 31. An isolation region forming method comprising: forming asilicon nitride layer over a substrate, the silicon nitride layer havinga pattern of openings extending therethrough to expose portions of theunderlying substrate; etching the exposed portions of the underlyingsubstrate to form openings extending into the substrate; after etchingthe exposed portions of the underlying substrate, wet etching thesilicon nitride layer to remove portions the silicon nitride layer whileleaving other portions of the silicon nitride layer over the substrate;and after the wet etching, forming oxide within the openings in thesubstrate, the oxide within the openings forming at least portions ofisolation regions.
 32. The method of claim 31 further comprising:forming a silicon oxide layer over the substrate; and the forming thesilicon nitride layer comprising forming the silicon nitride layer overthe silicon oxide layer.
 33. The method of claim 31 wherein said otherportions of the silicon nitride layer have a thickness of at least about600 Åafter the wet etching.
 34. The method of claim 31 the wet etchingcomprises exposing the silicon nitride layer to phosphoric acid.
 35. Anisolation region forming method comprising: forming a silicon nitridelayer over a substrate; forming a masking layer over the silicon nitridelayer; forming a pattern of openings extending through the masking layerto the silicon nitride layer; extending the openings through the siliconnitride layer to the underlying substrate with a first etch, the siliconnitride layer comprising edge regions proximate the openings and havinga central region between the edge regions; extending the openings intothe underlying substrate with a second etch, the second etch forming apolymer over the edge regions; after extending the openings into theunderlying substrate, exposing the silicon nitride layer and maskinglayer to dry etching conditions to remove the polymer from the edges ofthe silicon nitride layer and to remove portions of the masking layerwhile leaving other portions of the masking layer remaining over thesilicon nitride layer; after the dry etching, further extending theopenings into the substrate; and after the further extending, formingoxide within the openings in the substrate, the oxide within theopenings forming at least portions of isolation regions.
 36. The methodof claim 35 wherein the second etch comprises different conditions thanthe first etch.
 37. The method of claim 35 wherein the second etchcomprises a dry plasma etch utilizing CF₄/HBr and the first etchcomprises a dry plasma etch utilizing at least one of CF₄ and CH₂F₂. 38.The method of claim 35 further comprising: forming a silicon oxide layerover the substrate; and the forming the silicon nitride layer comprisingforming the silicon nitride layer over the silicon oxide layer.
 39. Themethod of claim 35 wherein the dry etching comprises exposing thesilicon nitride layer and masking layer to an oxygen-containing gas. 40.The method of claim 35 wherein the masking layer comprises photoresistand the dry etching comprises exposing the silicon nitride layer andmasking layer to an oxygen-containing gas.
 41. The method of claim 35wherein the dry etching comprises exposing the silicon nitride layer andmasking layer to O₂.
 42. An isolation region forming method comprising:forming a silicon nitride layer over a substrate; forming a maskinglayer over the silicon nitride layer; forming a pattern of openingsextending through the masking layer to the silicon nitride layer;extending the openings through the silicon nitride layer to theunderlying substrate, the silicon nitride layer having edge regionsproximate the openings and having a central region between the edgeregions; extending the openings into the underlying substrate; afterextending the openings into the underlying substrate, reducing athickness of the silicon nitride layer at the edge regions to thin theedge regions relative to the central region; and forming oxide withinthe openings extended into the substrate, the oxide within the openingsforming at least portions of isolation regions.
 43. The method of claim42 further comprising forming a silicon oxide layer over the substrate,the forming the silicon nitride layer comprising forming the siliconnitride layer over the silicon oxide layer.
 44. The method of claim 42wherein a thickness of the cental region is substantially unchanged asthe thickness of the edge regions is reduced.
 45. The method of claim 42wherein the reducing the thickness of the silicon nitride layer at theedge regions comprises: removing a portion of the masking layeroverlying the silicon nitride layer edge regions while leaving anotherportion of the masking layer overlying the silicon nitride centralregion; and after removing the portion of the masking layer, and whilesaid other portion of the masking layer is over the silicon nitridecentral region, exposing the silicon nitride layer to etching conditionswhich reduce the thickness of the silicon nitride layer at the edgeregions.
 46. The method of claim 45 wherein the etching conditionsanisotropically etch the silicon nitride layer.
 47. The method of claim42 wherein the reducing the thickness of the silicon nitride layer atthe edge regions comprises: removing the masking layer; and facetetching the silicon nitride layer to form faceted edges at the edgeregions.
 48. The method of claim 42 further comprising: forming asilicon oxide layer over the substrate; the forming the silicon nitridelayer comprising forming the silicon nitride layer over the siliconoxide layer; after forming the silicon nitride layer and extending theopenings into the underlying substrate, removing a portion of thesilicon oxide layer underlying the silicon nitride layer edge regions toundercut the edge regions; and the reducing the thickness of the siliconnitride layer at the edge regions comprising: removing the maskinglayer; and facet etching the silicon nitride layer to form faceted edgesat the edge regions.